There has been a dramatic increase in the use of integrated circuits (IC's) over the last decade which resulted in an increased demand for greater complexity, higher operating speeds, and smaller device dimensions in the IC's. A number of methods are known to increase the integration density of integrated circuits. Considerable improvements have been achieved mainly by decreasing photolithographic defect densities. By using electron and X-ray exposure methods instead of the hitherto used light radiation, progress was made in the direction of higher resolution. There were, furthermore, efforts to reach very narrow line widths in the sub-micron range by extending conventional lithographic processes, rather than utilizing the cost-intensive techniques of electron and X-ray lithography. With the technique of plasma, or reactive ion, etching for etching metals and semi-conductive and dielectric materials, further developments took place in the direction of very narrow line widths and, therefore, improved device performance.
A number of publications and patents describe the so-called sidewall technology by means of which structures in the sub-micron range can be made. In U.S. Pat. No. 4,256,514, a method for forming a narrow dimensioned region on a silicon body is described that involves forming, on the silicon body, regions having horizontal surfaces and substantially vertical surfaces. A thin conformal layer is formed, both on the horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to remove the horizontal layer while leaving the vertical layer substantially intact. These vertical sidewalls define very narrow dimensioned regions on the silicon body.
A further development is disclosed in U.S. Pat. No. 4,502,914. Here structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a conformal silicon nitride or oxide layer is plasma deposited and subjected to reactive ion etching methods such that its horizontal regions and the polymeric structures are removed, with merely the narrow regions of the silicon nitride or oxide layer, that has originally been arranged adjacent to the vertical surfaces of the polymeric structures, remaining. The vertical sidewall structures are then converted into a mask with the same dimensions but consisting of a different mask material.
The basic concept of using a sidewall stud of sub-micron width as a mask for processing underlying layers, i.e., the "image transfer" concept, has also been applied in a process described in the IBM Technical Disclosure Bulletin article "Method for Making Sub-Micron Dimensions in Structures Using Sidewall Image Transfer Techniques" (Vol. 26, No. 9, February 1984, pp. 4587-4589). This process involves the deposition of a conformal Si.sub.3 N.sub.4 layer over a resist pattern and subsequent reactive ion etching which leaves a Si.sub.3 N.sub.4 sidewall at the vertical resist edges. Removal of the resist results in the self-standing studs which can be used as a mask to, for example, define an FET gate of sub-micron gate length.
Another sidewall technique that can be employed to produce sub-micron features is described in IBM Technical Disclosure Bulletin article "Precision-Sub-Micron-Dimensioned Mask for X-Ray Lithography" (Vol. 24, No. 7B, December 1984, pp. 4115-4117). Here, the oxide that grows on the vertical walls of patterned polysilicon films is used as a mask.
In contrast to these known processes, where the sidewalls are formed on the vertical surfaces of a profile, the sidewalls formed with the process disclosed by the present invention, and which eventually determine the sub-micron dimensions, are produced within the vertical surfaces of a polymeric resist profile. The sidewalls are produced in a silylation process which makes the exposed polymeric material of the profile substantially more etch resistant. The sidewall thickness is determined by the parameters of the silylation process. The rather complex hitherto known technique of forming thermally stable patterns and subsequently depositing a conformal layer, from which the sidewalls are obtained, is eliminated.
Silylation is defined as the replacement of an active hydrogen of a protic material (--OH, --NH, --SH) with a substituted silicon atom. The silylation of organic compounds is a technique that has been known but has only recently been used to alter the development rate of resists and to improve the resistance to reactive ion etching (RIE) in O.sub.2 plasma.
Silylation processes as well as the polymeric materials and silylation agents that can be used have been described in a number of references. Representative art citations, with regard to the application of silylation techniques in IC fabrication, are given below. Each of the cited reference are assigned to the present assignee and the teachings located therein are hereby incorporated by reference.
U.S. patent application Ser. No. 679,527 describes a method for producing multi-layer, plasma-developable resists which are capable of providing sub-micron resolution. In the teachings, the upper portion of a layer of polymeric material that has been exposed to patterned radiation is converted into a dry etch resistant form using a silylation process. Specific polymeric materials that can be employed, are defined therein.
U.S. Pat. No. 4,552,833 relates to a process for producing a negative-tone resist image. The image is produced by the successive steps of: first, exposing a film to a pattern of radiation, the film having such a composition that, upon exposure to radiation, the film comprises a polymer which can react with an organometallic reagent; then, treating the exposed film with an organometallic reagents and, finally developing a relief image by further treating the exposed film with an oxygen plasma. Preferred polymers and organometallic reagents are given.
In U.S. patent application Ser. No. 713,370 a method for creating multilayer patterned films is disclosed wherein at least one layer is etch resistant. This layer is obtained by silylating a patterned polymeric film in an organometallic reagent. The pattern is subsequently transferred using an oxygen plasma or equivalent dry-etch method.
U.S. patent application Ser. No. 713,509 describes a process for obtaining plasma resistant polymeric materials as well as their uses in lithography. The materials are prepared by reacting a polymeric material with an organometallic silylation agent such as HMCTS, hexamethylcyclotrisilazane.
The above cited references are representative of the present use of silylation techniques in the fabrication of integrated circuits. These known processes are used to form etch-resistant silylated resist layers but do not suggest any application in the formation of sidewalls as proposed in the present invention.